Fig. 8 Vd and Vsc0 vs. Pout
Fig 9 u vs. out.
Fig. 10 THD vs. out.
Fig. 11 Vd and Vsc0 vs. Pout.
5. STEADY-STATE CHARACTERISTICS
Let us discuss here the steady-state characteristics of the proposed system with duplex reactor on the basis of the theory derived so far.
Fig. 8 shows the characteristics of dc link voltage Vd and synchronous compensator terminal voltage Vsc0 versus output power Pout for the case of constant output voltage and constant power factor of the load. The characteristics for the conventional system with AC reactor are also shown for the sake of comparison. From the figure, it is shown that Vd and Vsc0 increase greatly with output power for the case of proposed system. In this case, when output terminal voltage is kept constant, since the voltage at the imaginary terminal u in Fig. 4 (Vμ) should increase because of voltage drop in Lγ Vd and Vsc0 increase with Pout accordingly. The measured and calculated results are in good agreement, supporting the appropriateness of the theory.
In Fig. 9 the characteristics of the angle of overlap of inverter output currents u , with which operation limit is determined, versus output power Pout for the tested system are shown. It is shown from the figure that the increase in u is suppressed greatly for the case with duplex reactor. This is because Vμ becomes larger for the proposed system. Hence, we can say that when the proposed system is used the operation limit of the system can be enlarged with the increases in system voltages.
Fig. 10 gives the characteristics of THD of the output voltage versus Pout for the tested system. It is shown that THD increases with d as mentioned in Fig, 7. The measured THD for the system with duplex reactor was below 5% for all cases, showing usefulness of the proposed system.
6. SUPPRESSION OF VOLTAGE INCREASE WITH CAPACITORS
The voltage increases for the system with duplex reactor should be suppressed to lessen the voltage ratings of the system. We propose here a simple method of suppressing the voltage increases in the system. The insertion of a set of capacitors in series with the output terminals makes it possible to reduce the voltages.